1. Field of the Invention
The present invention relates to a system clock distributing apparatus and a system clock distributing method for controlling a clock generation for a data transmission in a multiprocessor system.
2. Description of Related Art
Multiprocessor server systems have been developed is advanced in recent server systems, and there is a trend toward the further larger scale systems. In such a multiprocessing system, a data transmission except an IO system is required to be a high throughput and low latency in order to speed up a computing process. In view of this demand, it is a key not to use a serial transmission that is generally used in a recent high speed IO, but to transmit a large amount of units of data in a line and to make a transmission side chip and a reception side chip synchronously transmit data in a certain range.
Here, an inter-chip data transmission unit for performing a data transmission between chips will be described. FIG. 4 is a block diagram showing an example of a construction of the inter-chip data transmission unit. The inter-chip data transmission unit has a transmission side chip 130 and a reception side chip 140. The reception side chip 140 has a data writing unit 141, a ring buffer 142, and a data reading unit 143. The same system clock and synchronizing signal are supplied from an external unit to the transmission side chip 130 and the reception side chip 140.
The transmission side chip 130 transmits an inputted system clock as a writing clock to the reception side chip 140, latches the inputted synchronizing signal and the transmitting data with respect to the system clock, and transmits the inputted synchronizing signal and the transmitting data to the reception side chip 140. The data writing unit 141 writes the data from the transmission side chip 130 to the ring buffer 142 at the timing of the writing clock. The data writing unit 141 resets a writing pointer for designating a writing position according to the synchronizing signal from the transmission side chip 130 latched by the writing clock, and instructs the ring buffer 142. The data reading unit 143 reads out the data of the ring buffer 142 at the timing of the system clock. The data reading unit 143 resets the reading pointer for designating a reading position according to the synchronizing signal from an external unit latched by the system clock, and instructs the ring buffer 142.
According to the above-mentioned inter-chip data transmission unit, accurate writing can be performed by sending, from the transmission side chip 130 to the reception side chip 140, the writing clock with the synchronizing signal and the data, and accurate reading can be performed by sending the system clock and the synchronizing signal from the external unit to the transmission side chip 130 and the reception side chip 140.
Next, in the case where the above-mentioned inter-chip data transmission unit is applied to a multiprocessor system, a distribution of the system clock and the synchronizing signal to the respective chips on each substrate will specifically be described. FIG. 5 is a block diagram showing an example of a construction of a system clock distributing apparatus in a conventional multiprocessor system. FIG. 5 shows only a connection relating to the clock and the synchronizing signal. This system clock distributing apparatus has an oscillator 1, a PLL (Phase Locked Loop) 102, a clock distributor 103, a plurality of system boards 104, a crossbar board 105, and a back plane 6. The system clock (period T) and the synchronizing signal (period nT) are generated by the PLL 102 on the basis of the signal generated from the oscillator 1, and distributed from the clock distributor 103 to the system board 104 and the crossbar board 105 through the back plane 6.
FIG. 6 is a block diagram showing an example of a construction of a conventional system board. FIG. 6 shows only a connection relating to the clock and the synchronizing signal. The system board 104 has a clock regulator 111, an NB (north bridge) 112, a plurality of CPUs (Central Processing Unit) 113, and a plurality of MACs (Memory Access Controller) 114. The clock regulator 111 receives the system clock and the synchronizing signal from the clock distributor 103, regulates a delay time of the system clock by using the synchronizing signal, and distributes the system clock and the synchronizing signal to the NB 112 and the plurality of MACs 114. The NB 112 controls communication with the CPUs 113, the MACs 114, and other NBs, and distributes the system clock and the synchronizing signal received from the clock regulator 111 to the CPU 113. The CPU 113 accesses to a memory (not shown) connected to each MAC 114, and conducts a computing process. The MAC 114 controls an access from the CPU 113 to the memory.
FIG. 7 is a block diagram showing an example of a construction of a conventional crossbar board. FIG. 7 shows only a connection relating to the clock and the synchronizing signal. The crossbar board 105 has a clock regulator 121, and a plurality of XBs (Cross Bar) 122. The clock regulator 121 receives the system clock and the synchronizing signal from the clock distributor 103, regulates a delay time of the system clock by using the synchronizing signal, and distributes the system clock and the synchronizing signal to the plurality of XBs 122. The XB 122 connects between the NB 112.
In a system for sending simultaneously the system clock and the synchronizing signal from the clock distributor 103 as described above, when a skew, that is a deviation of the delay time in the system clock and the synchronizing signal increases, a normal operation cannot be conducted. Therefore, firstly, lengths of wirings are equalized from the clock distributor 103 to each chip. Since unevenness of an element, a substrate, or the like exists, it is difficult to suppress the skew of the clock of high frequency only by the equalization of the lengths. If the frequency of the system clock is low, the reduction in the skew is easy, however the system clock is a central clock of a server, and hence a high frequency is required. Then, to further reduce the skew, the clock regulators 111 and 121 on each substrate regulate the delay time by giving a delay amount set at each route from the outside to the system clock and the synchronizing signal.
As a conventional art relating to the present invention, for example, Patent reference 1 shown below is known. This clock supply system operates an LSI in a substrate by using a global clock supplied from an outside source instead of the local clock in the substrate. The substrate can be operated even when the global clock is cut off due to an accident, or at the time of a test of a single substrate.
[Patent Reference 1]
Japanese Patent Application Laid-Open Publication No. 9-233060 (Pages 3-5, FIG. 1)
However, since the clock regulators 111, 121 are required to operate as fast as other chips and are a special purpose chip, manufacturing cost of the apparatus becomes very high. Further, since it is necessary to externally adjust the delay time for each route, man-hour becomes very large. Therefore, even if the skew is suppressed to certain degree, its cost demerit is large. Furthermore, even if the adjustment is executed, it might not fall always within an adjustable range, resulting in a lowering of the go-through rate.